low power dtmf receiver s5t3170 1 introduction the s5t3170 is a complete dual tone multiple frequency (dtmf) receiver that is fabricated by low power cmos and the switched- capacitor filter technology. this lsi consists of band split filters, which separates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. it decodes all 16 dtmf tone pairs into a 4bits digital code. the externally required components are minimized by on chip provision of a differential input amp, clock oscillator and latched three state interface. the on chip clock generator requires only a low cost tv crystal as an external component. features detects all 16 standard tones. low power consumption: 15mw (typ) single power supply: 5v uses inexpensive 3.58mhz crystal three state outputs for microprocessor interface good quality and performance for using in exchange system power down mode/input inhibit ordering information applications device package operating S5T3170X01-d0b0 18 ? dip ? 300a ? 25 c to + 75 c S5T3170X01-s0b0 20 ? sop ? 375 pabx key phone system central office answering phone paging systems home automation system remote control mobile radio credit card systems remote data entry 18 ? dip ? 300a 20 ? sop ? 375
s5t3170 low power dtmf receiver 2 pin configuration pin description pin no symbol description 1 in + non inverting input of the internal amp. 2in ? inverting input of the internal amp. 3 gs gain select. the output used for gain adjustment of analog input signal with a feedback resistor. 4v ref reference voltage output (v dd /2, typ) can be used to bias the internal amp input of v dd /2. 5i in input inhibit. high input states inhibits the detection of tones. this pin is pulled down internally. 6 pdn control input for the stand-by power down mode. power down occurs when the signal on this input is in high states. this pin is pulled down internally. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 s5t3170 in+ in- gs v ref i in pdn osc1 osc2 gnd v dd si/gto eso dso q4 q3 q2 q1 oe (18-dip) 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 s5t3170 in+ in- gs v ref i in pdn osc1 osc2 gnd v dd si/gto eso dso q4 q3 q2 q1 10 11 nc oe nc (20-sop)
low power dtmf receiver s5t3170 3 absolute maximum ratings 7, 8 osc1 osc2 clock input/output. a inexpensive 3.579545mhz crystal connected between these pins completes internal oscillator. also, external clock can be used. 9 gnd ground pin. 10 oe output enable input. outputs q1-q4 are cmos push-pull when oe is high and open circuited (high impedance) when disabled by pulling oe low. internal pull up resistor built in. 11 - 14 q1 - q4 three state data output. when enabled by oe, these digital outputs provide the hexadecimal code corresponding to the last valid tone pair received. 15 dso delayed steering output. indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. presents a logic high when a received tone pair has been registered and the output latch is updated. returns to logic low when the voltage on si/gto falls below v th . 16 eso early steering outputs. indicates detection of valid tone output a logic high immediately when the digital algorithm detects a recognizable tone pair. any momentary loss of signal condition will cause eso to return to low. 17 si/gto steering input/guard time output. a voltage greater the v ts detected at si causes the device to register the detected tone pair and update the output latch. a voltage less than v ts frees the device to accept a new tone pair. the gto output acts to reset the external steering time constant, and its state is a function of eso and the voltage on si 18 v dd power supply (+5v, typ) characteristics symbol value unit power supply voltage v dd 6v analog input voltage range v i (a) ? 0.3 to v dd + 0.3 v digital input voltage range v i (d) ? 0.3 to v dd + 0.3 v output voltage range v o ? 0.3 to v dd + 0.3 v current on any pin i i 10 v operating temperature t opr ? 40 to + 85 ma storage temperature t stg ? 60 to + 150 c pin description (continued) pin no symbol description
s5t3170 low power dtmf receiver 4 electrical characteristics (v dd = 5v, ta = 25 c, unless otherwise noted) characteristic symbol test conditions min. typ. max. unit operating voltage v dd ? 4.75 ? 5.25 v operating current i dd ?? 3.0 9.0 ma power dissipation p d ?? 15 45 mw input voltage low v il ??? 1.5 v input voltage high v ih ? 3.5 ?? v input leakage current i i (lkg) v in = gnd or v dd ? 0.1 ? m pull up current on oe pin i pu oe = gnd ? 7.5 15 a analog input impedance r i f in = 1khz 8 10 ? m ? steering input threshold voltage v th ? 2.2 ? 2.5 v output voltage low v ol no load ?? 0.03 v v oh no load 4.97 ?? v output current (sinking) i o (sink) v ol = 0.4v 1 2.5 ? ma output current (sourcing) i o (source) v oh = 4.6v 0.4 0.8 ? ma v ref output voltage v o (ref) ? 2.4 ? 2.8 v v ref output resistance r o (ref) ?? 10 ? k ? analog input offset voltage v io ?? 25 ? mv power supply rejection ratio psrr gain setting amp at 1khz ? 60 ? db common mode rejection ratio cmrr ? 3.0v < v in < 3.0v ? 60 ? db open loop voltage gain g v gain setting amp at 1khz ? 65 ? db open loop unit gain bandwidth bw ?? 1.5 ? mhz analog output voltage swing v o (p-p) r l = 100k ? 4.5 ? v p-p acceptable capacitive load c l gs ? 100 ? pf acceptable resistive load r l gs ? 50 ? k ? analog input common mode voltage range v cm no load ? 3.0 ? v p-p valid input signal range (each tone of composite signal) v i(val) ?? 29 ? 1.0 dbm dual tone twist accept tw ?? 10 ? db acceptable frequency deviation ? f ??? 1.5% 2hz ? frequency deviation reject ? f r ? 3.5% ???
low power dtmf receiver s5t3170 5 notes : 1. digit sequence consists of all 16 dtmf tones. 2. tone duration = 40ms, tone pause = 40ms. 3. nominal dtmf frequencies are used. 4. both tones in the composite signal have an equal amplitude. 5. tone pair is deviated by 1.5% 2hz. 6. bandwidth limited (3khz) gaussian noise. 7. the precise dial tone frequencies are (350hz and 440hz) 2%. 8. for an error rate of better than 1 in 10000. 9. referenced to lowest level frequency component in dtmf signal. 10. minimum signal acceptance level is measured with specified maximum frequency deviation. 11. this item also applies to a third tone injected onto the power supply. 12. referenced to fig. 1 input dtmf tone level at -28dbm. third tone tolerance t3rd ?? 25 ? 16 ? db noise tolerance tn ??? 12 ? db dial tone tolerance dt ? 18 22 ? db crystal clock frequency f ck ? 3.5759 3.5795 3.5831 mhz maximum clock input rise time t r(max) external clock ?? 110 ns maximum clock input fall time t f(max) external clock ?? 110 ns acceptable clock input duty cycle d ck external clock 405060 % acceptable capacitive load d l osc2 pin ?? 30 pf tone present detect time t det(p) ? 51114ms tone absent detect time t det(a) ? 0.5 4 8.5 ms minimum tone duration accept t tda(min) user adjustable ?? 40 ms minimum tone duration reject t tdr(max) user adjustable 20 ?? ms acceptable interdigit pause t idp(a) user adjustable ?? 40 ms rejectable interdigit pause t idp(r) user adjustable 20 ?? ms propagation delay time si to q t d(si-q) oe = high ? 811 s propagation delay time si to dso t d(si-d) oe = high ? 12 16 s output data setup q to dso t su oe = high ? 3.4 ? s propagation delay time oe to q (enable) t d(qe-q)en rl = 10k, cl = 50pf ? 50 60 ns propagation delay time oe to q (disable) t d(qe-q)dis rl = 10k, cl = 50pf ? 300 ? ns electrical characteristics (continued) (v dd = 5v, ta = 25 c, unless otherwise noted) characteristic symbol test conditions min. typ. max. unit
s5t3170 low power dtmf receiver 6 test circuit figure 1. test circuit hl74ls47 3 b c lt rdo abi d gnd v cc f g a c d hl74hctls02 8 14 12 11 9 1 4 7 1 10 2 6 13 4 5 8 7 2 3 5 6 r3 c1 300k led kt3170 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 100k r2 r1 100k x - tal 2 0.1 f 3 2 1 456 7 89 0 * # 9 8 7 6 5 4 3 2 10 11 12 13 14 15 16 17 18 1 x - tal 1 v cc v cc v cc v cc a 1 lts542r com d 45 c dp 23 v cc 10 9876 g com f ab 16 15 14 13 12 11 10 9 r10 r9 r8 r7 r6 r5 r4 v cc ks58006 fig. 2 s5t5820c s5t3170
low power dtmf receiver s5t3170 7 timing diagram figure 2. timing diagram dtmf input eso si/gto q1 - q4 dso oe dtmf #n dtmf #n + 1 decoded tone # (n - 1) t tdr (max) t tda (min) t idp (a) t idp (r) t det (p) t det (a) t pgt t agt t su t d (si-d) t d (oe-q) dis t d (oe-q) en v th dtmf #n + 1
s5t3170 low power dtmf receiver 8 digital output outputs q1-q4 are cmos push pull when enabled (eo = high) and open circuited (high impedance) when disabled by pulling eo = low. these digital outputs provide the hexadecimal code corresponding to the dtmf signals. the table below describes the hexadecimal. note: z : high impedance h : high logic level l : low logic level no low frequency high frequency oe q4 q3 q2 q1 1 697 1209 h 0 0 0 1 2 697 1336 h 0 0 1 0 3 697 1477 h 0 0 1 1 4 770 1209 h 0 1 0 0 5 770 1336 h 0 1 0 1 6 770 1477 h 0 1 1 0 7 852 1209 h 0 1 1 1 8 852 1336 h 1 0 0 0 9 852 1477 h 1 0 0 1 0 941 1336 h 1 0 1 0 * 941 1209 h 1 0 1 1 # 941 1477 h 1 1 0 0 a 697 1633 h 1 1 0 1 b 770 1633 h 1 1 1 0 c 852 1633 h 1 1 1 1 d 941 1633 h 0 0 0 0 any - - lzzzz
low power dtmf receiver s5t3170 9 application circuit all resistors are 1% tolerance all capacitors are 5% tolerance figure 3. single ended input configuration r3 = r2r5/(r2+r5), voltage gain = r5/r1 input impedance : 2 + (1/wc) 2 all resistors are 1% tolerance all resistors are 1% tolerance all capacitors are 5% tolerance figure 4. differential ended input configuration in+ in- gs v ref i in pdn osc1 osc2 gnd v dd si/gto eso dso q4 q3 q2 q1 oe 0.1uf 100k 100k 3.58mhz +5v 0.1uf 300k 1 2 3 4 10nf 100k c1 r1 10nf 100k c2 r2 r3 37.5k r2 60k v ref r5 100k gs in- in+ s5t3170 + _ r 1 2 2
s5t3170 low power dtmf receiver 10 figure 5. guard time adjustment figure 6. oscillator connection t pgt = (r1c) in (v dd /v dd -v th ) t agt = (rpc) in (v dd /v tst ) r p = r1r2/(r1 + r2) decreasing t agt (t pgt > t agt ) t pgt = (rpc) in (v dd /v dd -v th ) t agt = (r1c) in (v dd /v th ) r p = r1r2 (r1 + r2) decreasing t pgt (t pgt < t agt ) v dd si/gto eso r1 c r2 si/gto eso r1 r2 c s5t3170 osc1 osc2 30pf 3.579545mhz osc1 osc2 s5t3170 to osc1 of next s5t3170
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